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11.06.2016

experteer
München - PLL Design Engineer

München
Hardware - R&D, F&E - Senior Fachkraft / Projektleiter

Key Qualification see below Description The candidate should have demonstrated skill in the following areas: •Analog and/or digital PLLs for frequency synthesis and/or SERDES applications •Understanding of PLL loop dynamics and building blocks •Understanding of PLL jitter sources and modeling (RJ and DJ) •Design of several of the following PLL sub-blocks: oAnalog: charge-pump, loop-filter, VCO/DCO, regulators, references oDigital: high-speed dividers, level-shifters, synchronizers, PFD/TDC •Verification flows: oERC, EMIR, SIGEM, timing analysis (e.g. Nanotime), signal integrity/noise coupling, reliability (e.g. xBTI, aging, overstress), LEC, voltage/clock domain crossings •Trade-offs fo ...














 
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